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HM-6551
March 1997
256 x 4 CMOS RAM
Description
The HM-6551 is a 256 x 4 static CMOS RAM fabricated using self-aligned silicon gate technology. Synchronous circuit design techniques are employed to achieve high performance and low power operation. On chip latches are provided for address and data outputs allowing efficient interfacing with microprocessor systems. The data output buffers can be forced to a high impedance state for use in expanded memory arrays. The HM-6551 is a fully static RAM and may be maintained in any state for an indefinite period of time. Data retention supply voltage and supply current are guaranteed overtemperature.
Features
* * * * * * * * * * * Low Power Standby . . . . . . . . . . . . . . . . . . . . 50W Max Low Power Operation . . . . . . . . . . . . . 20mW/MHz Max Fast Access Time. . . . . . . . . . . . . . . . . . . . . . 220ns Max Data Retention . . . . . . . . . . . . . . . . . . . . . . . .at 2.0V Min TTL Compatible Input/Output High Output Drive - 1 TTL Load Internal Latched Chip Select High Noise Immunity On-Chip Address Register Latched Outputs Three-State Output
Ordering Information
PACKAGE Plastic DIP CERDIP TEMPERATURE RANGE -40oC to +85oC -40oC to +85oC 220ns HM3-6551B-9 HM1-6551B-9 300ns HM3-6551-9 HM1-6551-9 PKG. NO. E22.4 F22.4
Pinout
HM-6551 (PDIP, CERDIP) TOP VIEW
A3 1 A2 2 A1 3 A0 4 A5 5 A6 6 A7 7 GND 8 D0 9 Q0 10 D1 11 22 VCC 21 A4 20 W 19 S1 18 E 17 S2 16 Q3 15 D3 14 Q2 13 D2 12 Q1
PIN A E W S D Q
DESCRIPTION Address Input Chip Enable Write E5able Chip Select Data Input Data Output
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. http://www.intersil.com or 407-727-9207 | Copyright (c) Intersil Corporation 1999
File Number
2989.1
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HM-6551 Functional Diagram
A0 A1 A5 A6 A7 D0 D1 D2 D3 A LATCHED ADDRESS REGISTER 5 A 5 8 A A A A A GATED COLUMN DECODER AND DATA I/O D DATA OUTPUT Q D LATCHES D 3 A 3 L Q Q A Q2 A Q3 A 8 8 8 D Q A Q0 Q1 GATED ROW DECODER 32 32 x 32 MATRIX
E W S2 S1 L D SELECT Q LATCH
LATCHED ADDRESS REGISTER
A2
A3
A4
NOTES: 1. Select Latch: L Low Q = D and Q latches on rising edge of L. 2. Address Latches And Gated Decoders: Latch on falling edge of E and gate on falling edge of E. 3. All lines positive logic-active high. 4. Three-State Buffers: A high output active. 5. Data Latches: L High Q = D and Q latches on falling edge of L.
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HM-6551
Absolute Maximum Ratings
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +7.0V Input, Output or I/O Voltage . . . . . . . . . . . GND -0.3V to VCC +0.3V ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 1
Thermal Information
Thermal Resistance (Typical, Note 1) JA JC CERDIP Package . . . . . . . . . . . . . . . . 60oC/W 15oC/W Plastic DIP Package . . . . . . . . . . . . . . 75oC/W N/A Maximum Storage Temperature Range . . . . . . . . .-65oC to +150oC Maximum Junction Temperature Ceramic Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +175oC Plastic Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +150oC Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . +300oC
Operating Conditions
Operating Voltage Range . . . . . . . . . . . . . . . . . . . . . +4.5V to +5.5V Operating Temperature Range HM-6551B-9, HM-6551-9 . . . . . . . . . . . . . . . . . . . -40oC to +85oC
Die Characteristics
Gate Count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1930 Gates
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE: 1. JA is measured with the component mounted on an evaluation PC board in free air.
DC Electrical Specifications
VCC = 5V 10%; TA = -40oC to +85oC (HM-6551B-9, HM-6551-9) LIMITS
SYMBOL ICCSB
PARAMETER Standby Supply Current
MIN -
MAX 10
UNITS A mA A V A A V V V V
TEST CONDITIONS IO = 0mA, VI = VCC or GND, VCC = 5.5V E = 1MHz, IO = 0mA, VCC = 5.5V, VI = VCC or GND, W = GND VCC = 2.0V, IO = 0mA, VI = VCC or GND, E = VCC
ICCOP
Operating Supply Current (Note 1)
-
4
ICCDR
Data Retention Supply Current
-
10
VCCDR II IOZ VIL VIH VOL VOH
Data Retention Supply Voltage Input Leakage Current Output Leakage Current Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage TA = +25oC PARAMETER Input Capacitance (Note 2) Output Capacitance (Note 2)
2.0 -1.0 -1.0 -0.3 VCC -2.0 2.4
+1.0 +1.0 0.8 VCC +0.3 0.4 -
VI = VCC or GND, VCC = 5.5V VO = VCC or GND, VCC = 5.5V VCC = 4.5V VCC = 5.5V IO = 1.6mA, VCC = 4.5V IO = -0.4mA, VCC = 4.5V
Capacitance
SYMBOL CI CO NOTES:
MAX 6 10
UNITS pF pF
TEST CONDITIONS f = 1MHz, All measurements are referenced to device GND
1. Typical derating 1.5mA/MHz increase in ICCOP. 2. Tested at initial design and after major design changes.
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HM-6551
AC Electrical Specifications
VCC = 5V 10%; TA = -40oC to +85oC (HM-6551B-9, HM-6551-9) LIMITS HM-6551B-9 SYMBOL
(1) TELQV (2) TAVQV (3) TS1LQX (4) TWLQZ (5) TS1HQZ (6) TELEH (7) TEHEL (8) TAVEL (9) TS2LEL (10) TELAX (11) TELS2X (12) TDVWH (13) TWHDX (14) TWLS1H (15) TWLEH (16) TS1LWH (17) TELWH (18) TWLWH (19) TELEL
HM-6551-9 MIN 5 300 100 0 0 50 50 150 0 180 180 180 180 180 400 ns ns ns ns ns ns ns ns MAX 300 300 150 150 150 UNITS ns ns ns ns ns ns ns ns ns ns TEST CONDITIONS (Notes 1, 3) (Notes 1, 3, 4) (Notes 2, 3) (Notes 2, 3) (Notes 2, 3) (Notes 1, 3) (Notes 1, 3) (Notes 1, 3) (Notes 1, 3) (Notes 1, 3) (Notes 1, 3) (Notes 1, 3) (Notes 1, 3) (Notes 1, 3) (Notes 1, 3) (Notes 1, 3) (Notes 1, 3) (Notes 1, 3) (Notes 1, 3)
PARAMETER Chip Enable Access Time Address Access Time Chip Select 1 Output Enable Time Write Enable Output Disable Time Chip Select 1 Output Disable Time Chip Enable Pulse Negative Width Chip Enable Pulse Positive Width Address Setup Time Chip Select 2 Output Disable Time Address Hold Time Chip Select 2 Hold Time Data Setup Time Data Hold Time Chip Select 1 Write Pulse Setup Time Chip Enable Write Pulse Setup Time Chip Select 1 Write Pulse Hold Time Chip Enable Write Pulse Hold Time Write Enable Pulse Width Read or Write Cycle Time
MIN 5 220 100 0 0 40 40 100 0 120 120 120 120 120 320
MAX 220 220 130 130 130 -
NOTES: 1. Input pulse levels: 0.8V to VCC - 2.0V; Input rise and fall times: 5ns (max); Input and output timing reference level: 1.5V; Output load: 1 TTL gate equivalent, CL = 50pF (min) - for CL greater than 50pF, access time is derated by 0.15ns per pF. 2. Tested at initial design and after major design changes. 3. VCC = 4.5V and 5.5V. 4. TAVQV = TELQV + TAVEL.
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HM-6551 Timing Waveforms
(8) TAVEL A (10) TELAX VALID (19) TELEL TEHEL (7) E (9) TS2LEL S2 TELS2X (11) (9) TS2LEL TELEH (6) TELEL (7) (8) TAVEL NEXT
D TELQV (1) TAVQV (2) Q (3) TS1LQX S1 HIGH VALID OUTPUT TS1HQZ (5)
W TIME REFERENCE
-1
0
1
2
3
4
5
FIGURE 1. READ CYCLE TRUTH TABLE INPUTS TIME REFERENCE -1 0 E H S1 H X S2 X L W X H A X V D X X OUTPUTS Q Z Z FUNCTION Memory Disabled Addresses and S2 are Latched, Cycle Begins Output Enabled but Undefined Data Output Valid Outputs Latched, Valid Data, S2 Unlatches Prepare for Next Cycle (Same as -1) Cycle Ends, Next Cycle Begins (Same as 0)
1 2 3
L L
L L L
X X X
H H H
X X X
X X X
X V V
4
H
H
X
X
X
X
Z
5
X
L
H
V
X
Z
The HM-6551 Read Cycle is initiated by the falling edge of E. This signal latches the input address word and S2 into on chip registers, providing the minimum setup and hold times are met. After the required hold time, these inputs may change state without affecting device operation. S2 acts as a high order address and simplifies decoding. For the output to be read, E, S1 must be low and W must be high. S2 must have been latched low on the falling edge of E. The output
data will be valid at access time (TELQV). The HM-6551 has output data latches that are controlled by E. On the rising edge of E the present data is latched and remains in that state until E falls. Also on the rising edge of E, S2 unlatches and controls the outputs along with S1. Either or both S1 or S2 may be used to force the output buffers into a high impedance state.
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HM-6551 Timing Waveforms (Continued)
(8) TAVEL A (10) TELAX VALID TELEL (19) TEHEL (7) E (9) TS2LEL S2 TELS2X (11) (9) TS2LEL TELEH (6) TEHEL (7) (8) TAVEL NEXT
D
DATA VALID TWLEH (15) TELWH (17)
TWHDX (13)
W
TDVWH (12) TWLWH (18) TS1LWH (16) TWLS1H (14)
S1
TIME REFERENCE -1 0 1 2 3 4 5
FIGURE 2. WRITE CYCLE TRUTH TABLE TIME REFERENCE -1 0 1 2 3 4 5 H L L INPUTS E H S1 H X L L X H X S2 X L X X X X L H X X W X X A X V X X X X V D X X X V X X X OUTPUTS Q Z Z Z Z Z Z Z FUNCTION Memory Disabled Cycle Begins, Addresses and S2 are Latched Write Period Begins Data In is Written Write is Completed Prepare for Next Cycle (Same as -1) Cycle Ends, Next Cycle Begins (Same as 0)
In the Write Cycle the falling edge of E latches the addresses and S2 into on chip registers. S2 must be latched in the low state to enable the device. The write portion of the cycle is defined as E, W, S1 being low and S2 being latched simultaneously. The W line may go low at any time during the cycle, providing that the write pulse setup times (TWLEH and TWLS1H) are met. The write portion of the cycle is terminated on the first rising edge of either E, W, or S1. If a series of consecutive write cycles are to be executed, the W line may be held low until all desired locations have been written. If this method is used, data setup and hold times must be referenced to the first rising edge of E or S1. By
positioning the write pulse at different times within the E and S1 low time (TELEH), various types of write cycles may be performed. If the S1 low time (TS1LS1H) is greater than the W pulse plus an output enable time (TS1LQX), a combination read-write cycle is executed. Data may be modified an indefinite number of times during any write cycle (TELEH). The HM-6551 may be used on a common I/O bus structure by tying the input and output pins together. The multiplexing is accomplished internally by the W line. In the write cycle, when W goes low, the output buffers are forced to a high impedance state. One output disable time delay (TWLQZ) must be allowed before applying input data to the bus.
6-6
HM-6551 Test Load Circuit
DUT (NOTE 1) CL
IOH
+ -
1.5V
IOL
EQUIVALENT CIRCUIT
NOTE: 1. Test head capacitance includes stray and jig capacitance.
All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
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Sales Office Headquarters
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